The development of semiconductor technology is very fast, in particular, a semiconductor chip tends to miniaturization of the tendency. However, the function requirement of semiconductor dice also tends to the diversification. In other words, a smaller region of the semiconductor chip requires more input/out pads so as to the density of the pins is increased quickly. Thus, the semiconductor chip is difficult to package and the yield is to be decreased.
The mainly purpose of the packaged structure is for preventing the chip from the damage. However, each the plurality of chips is formed by cutting the wafer, and packaging and testing each the plurality of chips. In addition, another package technology, which is called “Wafer Level Package, WLP”, is used to package before the wafer is cut into a plurality of chips. The wafer level package technology has several advantages such as short production cycle, lower cost, and no under-filler.
Furthermore, based on the requirement of 3C consumer products is increased every year, and the requirement for the space and the size of the functional chip and the memory chip became more and more miniaturization. Accordingly the requirement of the multi-chips system in package (SiP) is also increased. However, during the wafer-level system-level packaging process, in addition to the use of sophisticated and expensive wafer bonding machine (chip bonder), such that each pads on the active surface of the chip is electrically connected accurately to the connecting terminal of the substrate, but also the chip is grounded to have the thickness is in range from 2 mil˜4 mil (about 50 to 100 microns) such that the chip would be damaged due to the wafer is bonded and electrically connected to the substrate. In addition to investment in expensive equipment and the manufacturing process yields also need to improve for system in package process of wafer level system-level,